1. Field of the Invention
The invention relates to the making of integrated circuits and it is aimed at proposing an original testing method as well as an integrated circuit wafer structure that can be used to implement this test.
Integrated circuit chips, which normally have sides measuring some millimeters, are made in batches on semiconductor wafers with diameters ranging from several centimeters to several tens of centimeters. Several tens, hundreds or thousands of chips are therefore manufactured together on one and the same wafer, and the wafer is sliced into individual chips at the end of manufacture. Then these chips are put into appropriate protective packages.
2. Description of the Prior Art
An essential stage of the manufacture is the testing, on a wafer, of all the chips. This test enables the defective chips to be rejected before they are encapsulated. This makes it possible to avoid adding to manufacturing costs by the unnecessary and costly encapsulation of defective chips.
The testing on wafer is done by means of a testing apparatus provided with a set of extremely fine tips that are applied to the input/output pads of each chip. These pads are the contact pads which will be used subsequently to enable the chip to communicate with the exterior.
The testing apparatus is therefore designed for the application, with precision, of the testing tips to the contact pads of a chip, the testing of this chip, the marking of the chip if it is defective, the shifting of the tips to the next chip, the carrying out of the test, etc.
This procedure is a lengthy one since it is repeated as many times as there are chips. In general, if the chip is a simple one, the test procedure may be simple, but there will be very many chips (e.g. several thousands of them) per wafer. And if the chip is a complex one there are fewer chips (e.g. several hundreds of them) per wafer, but the testing procedure for each chip is lengthier. In both cases, the time taken to test a wafer may be very long, so that the test becomes the main factor in the cost of the integrated circuits. The testing apparatus is very costly and the greater the time taken to test the wafers, the greater is the number of testing machines that will be required for a batch production of integrated circuits.
It is possible to conceive of a method for testing all the chips of a wafer in parallel since the procedures to be carried out on each chip are identical. However this would imply the need to make a machine having a number of testing tips that is equal to the product of the number of chips by the number of contact pads of each chip. For example, for a wafer with 1000 chips having 8 contacts each, there would have to be 8000 testing tips for the machine instead of 8 tips. The machine would be so costly that the financial advantage procured by the reduction in water-testing time would be entirely lost. Furthermore, it would be difficult to separate the signals sent back by the different chips in response to the signal sent by the testing apparatus, so that it would be difficult to identify the defective chips.
This is why, according to the invention, another approach is proposed to the testing of wafers.